Chip Operation Product Engineer - George Town

1. A bachelor's degree or above major in microelectronics, physics, or material science or electrical engineering.
2. 3 years experience on Si chip product engineering, prefer on digital chips. Experienced on interface with foundry or package house.
3. Understanding semiconductor fabrication and test flow. Knowledge of advanced CMOS, advanced package is a plus.
4. Knowledge on common CMOS Si and package failure, mechanism, and corrective action is a plus.
5. Knowledge on JEDEC reliability spec, qualification flow, and quality spec is a plus.
6. Familiar with common failure analysis methods such as SEM, X-Ray, EMMI, and SAT is a plus.
7. Skilled on statistical yield data analysis, and proficient on using YMS tools.
8. Have good communication skills and be proficient in reading and writing both English and Chinese.
9. Collaborate with chip and packaging design teams to conduct DFM (Design for Manufacturability) check to ensure Si and package manufacturability.
10. Work with product team to estimate the chip yield and set appropriate SKU combination binning scheme.
11. Interface foundry on Si fabrication, take charge of Si wafer NTO planning, performing WAT and yield analysis. Drive foundry on corrective actions for yield loss or quality degradation.
12. Interface OSAT on wafer bumping and assembly. Ensure bumping and substrate DFM inputs from OSAT be implemented into package design, and co-define process BKM with vendors and monitor process quality.
13. Perform chip level and package reliability qual with collaboration with internal product team and suppliers. Ensure chip package meeting application spec.
14. Working with ATE team on chip CP and FT test coverage and yield analysis. Monitor yield trend and identify failure mechanism by fast eFA and pFA. .
15. Assist the quality department in analyzing customer RMAs and provide technical and experimental suggestions.

We provide annual leave, sick leave, epf, socso & eis.